In the silicon exfoliation process, nanoelectronic devices are first fabricated on a standard silicon wafer. A nitride passivation layer this then grown on top of the nanoelectronic devices and a nickel layer is electroplated on top of the nitride in order to apply a compressive stress to the silicon. This stress initiates a crack approximately 10 µm below the top surface of the silicon wafer. This crack can then be propagated using a mechanical, wafer scale exfoliation tool developed in the NDML in order to produce a uniform 10 µm thick, extremely flexible, single crystal silicon film. This method is a cost effective and efficient method for creating high performance, flexible nanoelectronic devices. After exfoliation, the thin silicon films can be further processed to expose Through Silicon Vias (TSVs) and divide the film up into 10 µm by 10 µm chiplets for assembly into complex, 3D, hybrid electronic structures and devices.